Check the following system memory. (1) Configuration information %MW10.52 to %MW10.67 (WSM52 to 67) (2) Configuratio

Usually, set the CPU No. to 0. The CPU No. 0 works as a master of an SX bus system. In a multi-CPU system or a CPU redu

Filter instructions are system FBs. System FBs that can be equalized are limited to_ The last value of the edge detectio

During battery-less operation, previous fault information and other 'history of RAS' are not saved. Only the present RAS

Common memory 1 and common memory 2 are handled together in terms of timing. However, to maintain the uniqueness of data

To use conversion instructions from MICREX-F (instructions with the suffix '_MF') with SH2000 or SPH3000 series, the fol

Clock adjustment is initiated from CPU0 (operating) to other CPUs (standby). It takes place on a constant (1-minute) cyc

In a redundant system, both CPUs are identified as CPU0 and you cannot read a battery error of the standby CPU. Determin

When the common memory system is used, this can be achieved by handshaking with an application using part of the link me

When the power supply recovers to normal, the ALM contact automatically returns to the original position (open).

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GLOBAL > PLC > SPH

Latest FAQ

When I write parameter to LonWorks module (NP1L-LW1) using support tool for a LonWorks (NP4N-LNDF), what is the required cable?
When I set the high-speed counter module (NP1F-HC2) to the preset operation mode of the multi-functional counter FB, the preset is disabled in the ...
Are there any restrictions on the mounting position of the I/O modules and communication modules on the base? I'd like to place the communication m...
When using a communication module (NP1L-RS1/RS2/RS3/RS4/RS), the FB outputs R_STS 'C0' (Hardware error detected) during receiving. In this case, ho...
When I attempted to download a project to a CPU with user ROM card by using D300win, a message appeared saying 'Invalid loader command process!' an...

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FAQ within [ SPH ]

21-30 of Total 235

≪ 3 / 24page ≫

I use the hot plug base board with station No. setup function (Type_NP1BS-13D). When I remove a module, how can I identify the removed module in D3...

Check the following system memory. (1) Configuration information %MW10.52 to %MW10.67 (WSM52 to 67) (2) Configuration fault information %MW10.68 to %MW1... Show Detail
- No：1482
- Displayed Date：2023/04/25 19:00
- Category： Main unit
A CPU module has a rotary switch (0 to F) for setting the CPU No. on its front. What CPU No. should I set?

Usually, set the CPU No. to 0. The CPU No. 0 works as a master of an SX bus system. In a multi-CPU system or a CPU redundant system which uses multiple CPU ... Show Detail
- No：1504
- Displayed Date：2023/04/25 19:00
- Category： Main unit
I want to equalize filter instructions in a redundant system.

Filter instructions are system FBs. System FBs that can be equalized are limited to_ The last value of the edge detection FB, present counter value of the co... Show Detail
- No：1563
- Displayed Date：2023/04/25 19:00
- Category： Application
When you use battery-less operation on the SPH, is the history of RAS information recorded?

During battery-less operation, previous fault information and other 'history of RAS' are not saved. Only the present RAS information is displayed. Show Detail
- No：1579
- Displayed Date：2023/04/25 19:00
- Category： Main unit
With the common memory of FL-net, I set word data with common memory 2 and bit data with common memory 1. Please describe the timing of transmissio...

Common memory 1 and common memory 2 are handled together in terms of timing. However, to maintain the uniqueness of data including those in common memory 1 a... Show Detail
- No：1311
- Displayed Date：2023/04/25 19:00
- Category： Communication (Others)
I use MICREX-SX Programmer Standard (Type_NP4H-SWN). Is it compatible with CPU modules of old versions?

To use conversion instructions from MICREX-F (instructions with the suffix '_MF') with SH2000 or SPH3000 series, the following software version of the CPU is... Show Detail
- No：1314
- Displayed Date：2023/04/25 19:00
- Category： Support tool (Standard)
Does equalization (from an operating CPU to a standby CPU) of the internal clock take place automatically? If so, when does it take place?

Clock adjustment is initiated from CPU0 (operating) to other CPUs (standby). It takes place on a constant (1-minute) cycle at the time of and after system st... Show Detail
- No：1401
- Displayed Date：2023/04/25 19:00
- Category： Main unit
An address error occurs when I read a battery error of the standby CPU (CPU1) from the operating CPU (CPU0).

In a redundant system, both CPUs are identified as CPU0 and you cannot read a battery error of the standby CPU. Determine the condition of the standby CPU fr... Show Detail
- No：1572
- Displayed Date：2023/04/25 19:00
- Category： Application
With the FL-net module (NP1L-FL1/FL2/FL3), is there any way to confirm that the data sent from the node-A have actually been received by the node-B?

When the common memory system is used, this can be achieved by handshaking with an application using part of the link memory. Without handshaking, it is not... Show Detail
- No：1638
- Displayed Date：2023/04/25 19:00
- Category： Communication (Others)
Does the built-in ALM contact of the power supply module of SPH maintain its status (contact closed) even if the power supply recovers to normal af...

When the power supply recovers to normal, the ALM contact automatically returns to the original position (open). Show Detail
- No：1289
- Displayed Date：2023/04/25 19:00
- Category： Main unit